Low power A/D converter

ABSTRACT

A comparator is arranged to compare a series of analog voltage signal samples on a first capacitor with a voltage on a second capacitor which is linearly increased or decreased to equal the sample value. The comparator&#39;s single output freezes the count of the counter at counts which are proportional to the voltage of the respective samples. In this manner, analog to digital conversion can be accomplished using a single line between the analog and digital sides of a circuit, thereby reducing parasitic capacitance.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The invention of the present application may find application insystems such as are disclosed in U.S. patent application entitled“SUBCUTANEOUS ONLY IMPLANTABLE CARDIOVERTER-DEFIBRILLATOR AND OPTIONALPACER,” having U.S. Ser. No. 09/663,607, filed Sep. 18, 2000, pending,and U.S. patent application entitled “UNITARY SUBCUTANEOUS ONLYIMPLANTABLE CARDIOVERTER-DEFIBRILLATOR AND OPTIONAL PACER,” having U.S.Ser. No. 09/663,606, filed Sep. 18, 2000, pending, of which bothapplications are assigned to the assignee of the present application,and the disclosures of both applications are hereby incorporated byreference.

[0002] In addition, the foregoing applications are related to the U.S.patent application entitled “DUCKBILL-SHAPED IMPLANTABLECARDIOVERTER-DEFIBRILLATOR AND METHOD OF USE,” U.S. patent applicationentitled “CERAMICS AND/OR OTHER MATERIAL INSULATED SHELL FOR ACTIVE ANDNON-ACTIVE S-ICD CAN,” U.S. patent application entitled “SUBCUTANEOUSELECTRODE FOR TRANSTHORACIC CONDUCTION WITH IMPROVED INSTALLATIONCHARACTERISTICS,” U.S. patent application entitled “SUBCUTANEOUSELECTRODE WITH IMPROVED CONTACT SHAPE FOR TRANSTHORACIC CONDUCTION,”U.S. patent application entitled “SUBCUTANEOUS ELECTRODE FORTRANSTHORACIC CONDUCTION WITH HIGHLY MANEUVERABLE INSERTION TOOL,” U.S.patent application entitled “SUBCUTANEOUS ELECTRODE FOR TRANSTHORACICCONDUCTION WITH LOW-PROFILE INSTALLATION APPENDAGE AND METHOD OF DOINGSAME,” U.S. patent application entitled “SUBCUTANEOUS ELECTRODE FORTRANSTHORACIC CONDUCTION WITH INSERTION TOOL,” U.S. patent applicationentitled “METHOD OF INSERTION AND IMPLANTATION FOR IMPLANTABLECARDIOVERTER-DEFIBRILLATOR CANISTERS,” U.S. patent application entitled“CANISTER DESIGNS FOR IMPLANTABLE CARDIOVERTER-DEFIBRILLATORS,” U.S.patent application entitled “RADIAN CURVED IMPLANTABLECARDIOVERTER-DEFIBRILLATOR CANISTER,” U.S. patent application entitled“CARDIOVERTER-DEFIBRILLATOR HAVING A FOCUSED SHOCKING AREA ANDORIENTATION THEREOF,” U.S. patent application entitled “BIPHASICWAVEFORM FOR ANTI-BRADYCARDIA PACING FOR A SUBCUTANEOUS IMPLANTABLECARDIOVERTER-DEFIBRILLATOR,” and U.S. patent application entitled“BIPHASIC WAVEFORM FOR ANTI-TACHYCARDIA PACING FOR A SUBCUTANEOUSIMPLANTABLE CARDIOVERTER-DEFIBRILLATOR,” the disclosures of whichapplications are hereby incorporated by reference.

FIELD OF THE INVENTION

[0003] The subject invention relates to electronic circuitry and moreparticularly to analog-to-digital conversion circuitry particularlyapplicable to subcutaneous implantable cardioverter defibrillators.

BACKGROUND OF THE INVENTION

[0004] Defibrillation/cardioversion is a technique employed to counterarrhythmic heart conditions including some tachycardias in the atriaand/or ventricles. Typically, V electrodes are employed to stimulate theheart with electrical impulses or shocks, of a magnitude substantiallygreater than pulses used in cardiac pacing.

[0005] Defibrillation/cardioversion systems include body implantableelectrodes that are connected to a hermetically sealed container housingthe electronics, battery supply and capacitors. The entire system isreferred to as implantable cardioverter/defibrillators (ICDs). Theelectrodes used in ICDs can be in the form of patches applied directlyto epicardial tissue, or, more commonly, are on the distal regions ofsmall cylindrical insulated catheters that typically enter thesubclavian venous system, pass through the superior vena cava and, intoone or more endocardial areas of the heart. Such electrode systems arecalled intravascular or transvenous electrodes. U.S. Pat. Nos.4,603,705, 4,693,253, 4,944,300, 5,105,810, the disclosures of which areall incorporated herein by reference, disclose intravascular ortransvenous electrodes, employed either alone, in combination with otherintravascular or transvenous electrodes, or in combination with anepicardial patch or subcutaneous electrodes. Compliant epicardialdefibrillator electrodes are disclosed in U.S. Pat. Nos. 4,567,900 and5,618,287, the disclosures of which are incorporated herein byreference. A sensing epicardial electrode configuration is disclosed inU.S. Pat No. 5,476,503, the disclosure of which is incorporated hereinby reference.

[0006] In addition to epicardial and transvenous electrodes,subcutaneous electrode systems have also been developed. For example,U.S. Pat. Nos. 5,342,407 and 5,603,732, the disclosures of which areincorporated herein by reference, teach the use of a pulsemonitor/generator surgically implanted into the abdomen and subcutaneouselectrodes implanted in the thorax. This system is far more complicatedto use than current ICD systems using transvenous lead systems togetherwith an active can electrode and therefore it has no practical use. Ithas in fact never been used because of the surgical difficulty ofapplying such a device (3 incisions), the impractical abdominal locationof the generator and the electrically poor sensing and defibrillationaspects of such a system.

[0007] Recent efforts to improve the efficiency of ICDs have ledmanufacturers to produce ICDs which are small enough to be implanted inthe pectoral region. In addition, advances in circuit design haveenabled the housing of the ICD to form a subcutaneous electrode. Someexamples of ICDs in which the housing of the ICD serves as an optionaladditional electrode are described in U.S. Pat. Nos. 5,133,353,5,261,400, 5,620,477, and 5,658,321 the disclosures of which areincorporated herein by reference.

[0008] ICDs are now an established therapy for the management of lifethreatening cardiac rhythm disorders, primarily ventricular fibrillation(V-Fib). ICDs are very effective at treating V-Fib, but are therapiesthat still require significant surgery.

[0009] As ICD therapy becomes more prophylactic in nature and used inprogressively less ill individuals, especially children at risk ofcardiac arrest, the requirement of ICD therapy to use intravenouscatheters and transvenous leads is an impediment to very long termmanagement as most individuals will begin to develop complicationsrelated to lead system malfunction sometime in the 5-10 year time frame,often earlier. In addition, chronic transvenous lead systems, theirreimplantation and removals, can damage major cardiovascular venoussystems and the tricuspid valve, as well as result in life threateningperforations of the great vessels and heart. Consequently, use oftransvenous lead systems, despite their many advantages, are not withouttheir chronic patient management limitations in those with lifeexpectancies of >5 years. The problem of lead complications is evengreater in children where body growth can substantially altertransvenous lead function and lead to additional cardiovascular problemsand revisions. Moreover, transvenous ICD systems also increase cost andrequire specialized interventional rooms and equipment as well asspecial skill for insertion. These systems are typically implanted bycardiac electrophysiologists who have had a great deal of extratraining.

[0010] In addition to the background related to ICD therapy, the presentinvention requires a brief understanding of a related therapy, theautomatic external defibrillator (AED). AEDs employ the use of cutaneouspatch electrodes, rather than implantable lead systems, to effectdefibrillation under the direction of a bystander user who treats thepatient suffering from V-Fib with a portable device containing thenecessary electronics and power supply that allows defibrillation. AEDscan be nearly as effective as an ICD for defibrillation if applied tothe victim of ventricular fibrillation promptly, i.e., within 2 to 3minutes of the onset of the ventricular fibrillation.

[0011] AED therapy has great appeal as a tool for diminishing the riskof death in public venues such as in air flight. However, an AED must beused by another individual, not the person suffering from the potentialfatal rhythm. It is more of a public health tool than a patient-specifictool like an ICD. Because >75% of cardiac arrests occur in the home, andover half occur in the bedroom, patients at risk of cardiac arrest areoften alone or asleep and can not be helped in time with an AED.Moreover, its success depends to a reasonable degree on an acceptablelevel of skill and calm by the bystander user.

[0012] What is needed therefore, especially for children and forprophylactic long term use for those at risk of cardiac arrest, is acombination of the two forms of therapy which would provide prompt andnear-certain defibrillation, like an ICD, but without the long-termadverse sequelae of a transvenous lead system while simultaneously usingmost of the simpler and lower cost technology of an AED. What is alsoneeded is a cardioverter/defibrillator that is of simple design and canbe comfortably implanted in a patient for many years.

[0013] One factor which has added complexity to ICD design is thenecessity to digitize an analog electrocardiogram (ECG) signal. Forexample, it may be desired to sample an ECG signal at intervals of 2milliseconds or 4 milliseconds, i.e. at either a 250 Hz. or 500 Hz.sampling frequency.

[0014] Typically, an analog to digital converter (A/D) circuit isemployed in such applications. In some cases, the environment includesan analog chip optimized for analog functions and a digital chipoptimized for digital functions. Data may be transferred from the analogchip to the digital chip via, for example, an 8 bit A/D converteremploying various known A/D conversion techniques, for example,successive approximation techniques, resistive ladders, or slopeconverters. In such an application, there would typically be a bushaving 8 parallel lines connecting, for example, a microprocessor to anA/D converter located on an analog chip. A read/write control signal isthen used to bring all 8 bits over a digital bus to the microprocessor.

[0015] One problem with this approach is that each of the bus lines havea parasitic capacitance associated with them. With respect to an eightbit bus, from 1 to all 8 of the parallel bus lines may toggle up or downon each cycle. Every time a line toggles it is necessary to charge upand discharge the parasitic capacitance associated with that line. Thepower lost due to this parasitic capacitance may be represented by theexpression: $\begin{matrix}{\lbrack {\frac{n}{2} + 1} \rbrack \cdot {Cp} \cdot f \cdot V^{2}} & (1)\end{matrix}$

[0016] where “n” is the number of lines toggled, Cp is the value of theparasitic capacitance, f is the frequency, V is the voltage and “1”represents the parasitic capacitance associated with a read/write line,e.g., from a microprocessor. Equation (1) further employs the expressionN over 2 because, on average, only half the bus signals will changestate. If one increases the number of bits of the conversion to increaseresolution, additional power will be lost. In some cases, the power losscan be worse because, if 10 bits are transferred to an 8 bitmicroprocessor, two transfers would be required and possibly anotherread/write signal line.

SUMMARY OF THE INVENTION

[0017] According to the invention, the value of an analog voltage samplederived on an analog side of an interface is used to control a countdeveloped on a digital side of the interface. In this manner, a singlecontrol line crossing the analog/digital interface is used to develop acount corresponding to the value of the analog sample. In this manner,only a single signal line is subject to parasitic capacitance, asopposed to, for example, 8 or more parallel bus lines.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] For a better understanding of the invention, reference is nowmade to the drawings where like numerals represent similar objectsthroughout the figures and wherein:

[0019]FIG. 1 is an electrical circuit diagram of an illustrativeembodiment of the invention.

[0020]FIG. 2 is an electrical circuit diagram of illustrative logic foruse in implementing the analog side control block 33 of FIG. 1.

[0021]FIG. 3 is an electrical circuit diagram illustrative of logic foruse in implementing the digital side control block 49 of FIG. 1. FIG. 4is a waveform diagram useful in illustrating operation of the circuitryof FIG. 2.

[0022]FIG. 5 is a waveform diagram useful in illustrating operation ofthe circuitry of FIG. 3.

[0023]FIG. 6 is a schematic block diagram of an embodiment employing aprogrammed digital processor.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0024] An illustrative embodiment is shown in FIG. 1, wherein thecircuit is schematically divided by a line 15 into an analog side 17 anda digital side 19. The analog side 17 of the circuit includes acomparator 21 having an inverting input connected to a first terminal ofa first capacitor C₁ and a non-inverting input connected to the firstterminal of a second capacitor C₂. The second terminals of therespective capacitors C₁, C₂ are grounded.

[0025] The first terminal of the first capacitor C₁ is arranged to beconnected via operation of respective switches 23, 25 to either a firstcharging current source 27 or a second discharging current source 29.The switches 23, 25 are controlled by respective control signals B, A.

[0026] The second capacitor C₂ is arranged to capture a sample of ananalog input voltage Vi (t) which is to be converted to a digital valueby the circuit. The sample is provided by momentarily closing a switch31 in response to application of a third control signal C.

[0027] The three control signals A, B, C are provided by a controlcircuit 33, which receives a clock input CLK/N and an input from theoutput 35 of the comparator 21 which output 35 supplies a control signalUP/DOWN.

[0028] On the digital side 19 of the circuit, the output 35 of thecomparator 21 is supplied to an n-bit up-down counter 41, which providesa binary count on a number of parallel output lines 43 to a latchcircuit 45. The number of parallel lines 43 may be, for example, eightin number. The latch 45 is enabled to latch the count of the counter 41by a control signal LE supplied on a signal line 47 by control logic 49.This logic 49 receives input signals including the UP/DOWN controlsignal on line 35, a clock signal CLK, and a count signal. Thefunctionality of the digital side circuitry 19 can, if desired, beembodied as part of a programmed digital processor 100, e.g., amicroprocessor.

[0029] The clock signal CLK is a system clock signal, which may begenerated in conventional fashion. The signal is divided by a divisor Nat a divider block 51 to produce a signal denoted CLK/N. Again,production of such a clock and divided clock signals may be accomplishedby conventional techniques well-known in the art.

[0030] An illustrative example of operation of the circuit of FIG. 1will now be provided, assuming that the dynamic range of Vi(t) is zeroto one volt, that the capacitor voltages V₁ and V₂ are initially zero,and that the counter 41 is an 8 bit counter (0 to 255). Assuming Vi(t)rises to ½ volt and is sampled at that value by application of thecontrol signal C, the voltage on the sampling capacitor C₂ will behigher than that on the first capacitor C₁, which will result in a“true” or “positive” output from the comparator 21. The production of a“true” output turns on switch B, causing the current from the currentsource 29 to linearly charge the first capacitor C₁. The “true” signalon the output 35 further causes the up/down counter 41 to begin countingup. When the voltage on the first capacitor C₁, reaches the value of thevoltage on the second or sample capacitor C₂, the output 35 of thecomparator 21 changes state causing the count of the UP/DOWN counter 41to stop at a binary value representative of ½ volt, which is thencaptured by the latch 45. Thus, an eight bit count has been developed bya change of state on only one analog signal line 35.

[0031] Next, assume that at the next sample time, Vi(t) drops by 5millivolts. V_(C1) is then smaller than V_(C2), resulting in a false ornegative signal on the output 35 of the comparator 21, which causes theUP/DOWN counter 41 to begin counting down and further causes supply of acontrol signal A to the switch 25, thereby beginning to linearly reducethe voltage on the first capacitor C₁. When this voltage again equalsthe voltage on the sampling capacitor C₂, the signal count on thecomparator output 35 freezes the UP/DOWN counter 41, whose output isthen latched by the latch 45.

[0032] With respect to clock frequencies, a 32 KHz clock is a frequencytypical of those running on typical digital chips. For an eight bitUP/DOWN counter 42, the sample period is then 7.8 milliseconds. Thecontrol signal C thus has a frequency of 32.768 KHz/256=128 KHz.

[0033]FIG. 2 depicts illustrative control logic for implementing block33 of FIG. 1 so as to generate the sample signal C and control theoperation of the current sources 27, 29. This logic includes amonostable multivibrator 61, three flip-flops 63, 65, 67, two AND gates69, 71, an OR gate 73, and an inverter 75.

[0034] A conversion begins on each rising edge of the 128 Hz sampleclock shown in FIG. 4. The sample signal C is generated on this risingedge by the monostable 61. The {overscore (Q)} output 72 of themonostable 61 goes low on this rising edge, resetting the flip-flops 65and 67 such that their Q outputs are low and there is no “DONE” signalon the output of the OR gate 73. If the UP/DN signal from the comparator21 changes state, the Q output of one of the flip-flops 65, 67 will gotrue, such that the “DONE” output of the OR gate 73 will go true also.

[0035] The UP/DN signal also is supplied to the flip-flop 63 whose Q and{overscore (Q)} outputs form respective inputs to the two AND gates 69,71. Each of these gates 69, 71 receives the output of the inverter 75(“NOT DONE”) as its second input. Thus, the output B of the AND gate 69will be true if a comparison is underway and the comparator output 35 ispositive, while the output A of the AND gate 71 will be true if acomparison is underway and the comparator output 35 is negative. Asnoted above, when the comparator 21 changes state, i.e., when thevoltage or the capacitor C₂ equals the sample voltage, the DONE outputgoes true, thereby disabling the AND gates 69, 71 and, as the case maybe, terminating charging or discharging of the capacitor C₁.

[0036]FIG. 3 depicts illustrative control logic for implementing block49 of FIG. 1 so as to generate the latch enable signal LE and controlsupply of the COUNT signal to the UP/DOWN counter 41. This logicincludes three flip-flops 79, 81, 83, an inverter 85, an OR gate 87, aninverter 89, and an AND gate 91. The flip-flop 79 generates Q and{overscore (Q)} each cycle of the 128 Hz clock. The flip-flop 79 therebyresets the active low reset flip-flops 81, 83 on the rising edge of thesample clock pulse, and generates the latch enable signal LE on thefalling edge of the simple clock pulse.

[0037] The three input AND gate 91 controls the 32 KHz clock signalCOUNT provided to the up-down counter 41. The three inputs to the ANDgate 91 are the {overscore (Q)} output of the flip-flop 79, the 32 KHzclock signal, and the “NOT DONE” output of the inverter 89.

[0038] In operation of the logic of FIG. 3, when no conversion isunderway, the DONE signal is “true,” which gates off the clock as aresult of the “false” input provided by the inverter 89 to the AND gate91. When a conversion begins, the UP/DN signal input to the flip-flop 81causes the NOT DONE signal to go “true,” thereby permitting the 32 KHzclock signal to pass through the AND gate 91, thereby causing theUP/DOWN counter 41 to begin counting. When the output 35 of thecomparator 21 changes state, the input of the UP/DN signal to theflip-flop 81 causes the DONE signal to again go true, freezing the countof the counter 41 at a value representative of the value of the analogsample of V_(i(t)) currently held by the sample capacitor C₂.

[0039] While the present invention has been described above in terms ofspecific embodiments, it is to be understood that the invention is notlimited to the disclosed embodiments. On the contrary, the followingclaims are intended to cover various modifications and equivalentmethods and structures included within the spirit and scope of theinvention.

What is claimed is:
 1. An electrical circuit comprising: first means forstoring an analog sample of a first voltage; second means for storing anelectrical charge to develop a second voltage; charging means responsiveto a plurality of control signals for selectively charging anddischarging said means for storing to correspondingly increase or reducesaid second voltage; and means responsive to said first and secondvoltages for developing a binary count representative of the analogvalue of said first voltage.
 2. The circuit of claim 1 wherein saidmeans for developing a binary count comprises a comparator and anUP/DOWN counter.
 3. The circuit of claim 2 wherein, when said firstvoltage exceeds said second voltage, a first of said control signalscauses said charging means to increase said second voltage and, whensaid first voltage is less than said second voltage, a second of saidcontrol signals causes said charging means to reduce said secondvoltage.
 4. The circuit of claim 3 wherein said UP/DOWN counter countsup while said charging means is increasing said second voltage and stopscounting up when said first and second voltages become equal.
 5. Thecircuit of claim 4 wherein said UP/DOWN counter counts down while saidcharging means is decreasing said second voltage and stops counting downwhen said first and second voltages become equal.
 6. The circuit ofclaim 5 wherein the count of said counter when said counter stopscounting is a binary value representative of the value of the analogvoltage stored by said first means for storing.
 7. The circuit of claim6 residing in a subcutaneous implantable cardioverter-defibrillator andwherein said analog sample is a sample of an electrocardiogram signal.8. A method comprising the steps of: sampling an analog voltage signalto develop a series of voltage samples; and controlling the count of adigital counter to develop a series of counts, a respective one of theseries of counts being proportional to the value of a corresponding oneof said series of voltage samples.
 9. The method of claim 8 wherein saiddigital counter is controlled to develop said count by a single leadfrom an analog circuit.
 10. The method of claim 9 wherein said singlelead is the output of a comparator.
 11. The method of claim 10 whereinsaid comparator is operative to compare a first analog voltage sample toa second linearly changing voltage and to stop the count of said counterwhen said first and second voltages are equal.
 12. The electronicapparatus comprising: a comparator arranged to compare a series ofanalog voltage signal samples on a first capacitor with a second voltageon a second capacitor, the second voltage being linearly increased ordecreased to equal the sample value; and a counter whose count is frozenat counts which are proportional to the voltage of the respective signalsamples in response to an output from said comparator.
 13. The apparatusof claim 12 wherein said counter is an UP/DOWN counter.
 14. Theapparatus of claim 13 further including control logic responsive to anoutput of said comparator to control said second voltage.
 15. Theapparatus of claim 14 wherein said comparator and counter cooperate toperform A/D conversion.
 16. The apparatus of claim 12 further includinga programmed digital processor, said digital processor implementing saidcounter.
 17. The apparatus of claim 14 further including a programmeddigital processor programmed to implement said UP/DOWN counter and saidcontrol logic.
 18. The apparatus of claim 12 wherein a single outputline from said comparator interconnects an analog side of said apparatusincluding said comparator to a digital side of said apparatus includingsaid counter.
 19. The apparatus of claim 12 forming part of circuitrycomprising a subcutaneous implantable cardioverter-defibrillator andwherein said analog voltage samples comprise samples of anelectrocardiogram waveform.
 20. The method of claim 8 wherein said stepsare performed to accomplish analog-to-digital conversion in asubcutaneous implantable cardioverter-defibrillator.